Sense system for dynamic random access memory

摘要

A dynamic random access memory (DRAM) of 2/3 VDD precharge scheme is disclosed. A latch driving circuit controls the voltage of the common node of a sense latch so as to limit the downward voltage swing of bitlines to 1/3 VDD, a low level restore voltage. The sense latch is coupled to a pair of I/O data lines through PMOS FET column switches. This invention provides high speed memory operation and reduces power consumption.