CLOCK SYNCHRONIZATION SYSTEM

摘要

PURPOSE:To provide a clock synchronization system which can perform switching between the working and stand-by clock generating parts with an optional timing and without causing any waveform spike in the supplied clocks. CONSTITUTION:Clock generating parts 1a and 1b generating a device clock CLK1a and a device clock CLK1b respectively are mutually in the relation of active and stand-by. When the part 1a is operating, the CLK1a is used as a supplied clock CLK10. Each of both clock generating parts 10a and 10b generates a network synchronizing signal fS1 through an oscillation circuit 1 for generation of a clock fN and then divides this clock fN into the clocks CLK1 through a dividing circuit 2. This dividing timing synchronizes with a network synchronizing signal fS2 in an active mode and with a synchronizing pulse PLS2 in a stand-by mode respectively. The pulse PLS2 generates the signal fS2 by an extent equal to the width of a single clock fN.