| 摘要 |
<p>PURPOSE:To provide a semiconductor memory suitable for fine patterning in which the number of wiring per unit memory cell is decreased through a simple structure while allowing high speed writing and reading. CONSTITUTION:A floating conductive layer 14 doped with impurities, an undoped barrier layer 16, a channel layer 18, an undoped thin barrier layer 20, and a conductive layer 22 are formed sequentially on a semiconductor substrate 10 and then first and second electrodes 24, 26 are provided, respectively, on the conductive layer 22 and the channel layer 18. Information is written into the floating conductive layer 14 by applying a write bias voltage which is higher for the second channel 26 than for the first electrode 24. Stored information is read out by applying a read bias voltage which is lower for the second electrode 26 than for the first electrode 24. Information written into the floating conductive layer 14 is erased by applying a erasure voltage having absolute value larger than that of the read bias voltage.</p> |
