| 摘要 |
To ensure interference-free transmission of digital messages, very high demands are made on the accuracy and stability of the clock generators. It is known to use for this purpose microprocessor-controlled digital phase-locked loops and to use for this expensive highly stable crystal oscillators. An accurate system clock should be delivered even if the reference clock fails. Contradictory demands are made on the phase-locked loops, on the one hand a wide bandwidth to achieve a small phase timing error and on the other hand a narrow bandwidth in order to keep down the influence of jitter and wander on the clock accuracy when the reference clock fails. It is the object of the invention to specify a circuit arrangement for an inexpensive clock generator which should deliver a highly accurate clock frequency even when the reference clock fails. According to the invention, the contradictory demands on a phase-locked loop are distributed over two phase-locked loops, both of which are controlled by a microprocessor and which are allocated only one oscillator. A first phase-locked loop (1) having a narrow bandwidth is connected via a change-over switch (3) to a second phase-locked loop having a wide bandwidth. When the reference clock fails, the output clock of the first phase-locked loop (1) is switched as reference clock to the second phase-locked loop (2). <IMAGE> |
