| 摘要 |
<p>An integrated circuit device (10) for comparing (at C1 to C96) the state of a large number of inputs (1 to 32), i.e. "discretes", against any one of a plurality of selectable voltage levels. The compared data is examined in a 3x3 matrix format (CH1 FFD-1 to FFD-3, CH2 FFD-1 to FFD-3, CH# FFD-1 to FFD-3). In a redundant mode, comparators are utilized in a triple-redundant configuration to obtain a consensus on input states, at three successive time intervals, raising a flag when consensus fails. Inputs, whether in a redundant or non-redundant mode are distributed along three different sides of a rectangular-shaped substrate to prevent catastrophic mechanical failures. In the redundant mode, discretes are compared using a voting technique (V1) such that when all three levels are the same, an error free status is provided, whereas a two-out-of-three vote is interpreted as correct but with an indication that the discrete being monitored requires further checking. Data, fault and self-test results are made available to the outside world by a parallel/serial transmitter (SPC-1) and in parallel form by discrete output terminals (DATA {15:0}). Output data is compared with data inputted for further assuring integrity of the device (FAULT). Output data is selectable in either an eight bit or sixteen bit tri-state port (TS-1 to TS-12), which is addressable for channel data, status, bounds, mismatch, built-in self-test and major fault information. <IMAGE></p> |
