| 摘要 |
<p>A phase-locked loop circuit with holdover mode is formed utilizing a primary (3) and secondary (4) phase-locked loop circuits. Each loop circuit comprises a phase detector (20;60), loop filter (30;20), VCXO (40;80) and frequency divider (50;90). The secondary loop (4) is configured such that its output is very stable. The primary loop (3) is phase-locked on a received reference clock signal (Vref) and the second loop (4) is phase locked on the output (V0,N1) of the primary loop, the scaled output of the secondary loop being parallel to the reference clock signal. If the incoming reference signal is interrupted or lost the circuit is switched (by 8,10) to a holdover mode where the input (21) of the primary loop is switched to the stable scaled output of the secondary loop. In holdover mode, the output of the primary loop is phase-locked to the stable output of the secondary loop. When the reference clock signal is reestablished, the input of the primary loop is switched back (by 8,10) to the reference clock signal. <IMAGE></p> |
