发明名称 Packet disassembler for use in a control unit of an asynchronous switching system
摘要 A packet disassembler, which eliminates the need of an upper-level processor to have an excessive processing ability, includes a plurality of fixed-length buffers having a storage capacity corresponding to a multiple of the byte length of an information field of input packets having a predetermined fixed length and each of the fixed-length buffers has an identical length. Also included in the packet disassembler is manager which, when disassembling ones of the input packets having an identical connection identifier within their headers or having a multiplexing identifier on the same connection is not completed, performs allocation control of associating the packets having the identical identifier with one of the plurality of fixed-length buffers having the identical identifier, and when the disassembling of the packets having the identical identifier is completed or when no disassembling of the packets having the identical identifier is carried out, performs allocation control of associating the associated packets with an empty one of the plurality of fixed-length buffers.
申请公布号 US5414702(A) 申请公布日期 1995.05.09
申请号 US19930137927 申请日期 1993.10.19
申请人 KABUSHIKI KAISHA TOSHIBA 发明人 KUDOH, NORIMASA
分类号 H04L12/56;H04Q11/04;(IPC1-7):H04J3/24 主分类号 H04L12/56
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