发明名称 Voltage variation compensation arrangement for sample and hold capacitor
摘要 An analog multiplier generates an output signal that is coupled to a convergence winding of a projection television. The analog multiplier multiplies a horizontal rate sawtooth signal with a vertical rate parabola signal. The multiplier DC operating point is adjusted, by developing a DC voltage in a hold capacitor of a sample and hold arrangement during each vertical blanking interval. To prevent a change in the capacitor voltage during vertical trace, a vertical rate sawtooth signal is coupled to the hold capacitor via a second capacitor.
申请公布号 US5414329(A) 申请公布日期 1995.05.09
申请号 US19940219222 申请日期 1994.03.28
申请人 THOMSON CONSUMER ELECTRONICS, INC. 发明人 GEORGE, JOHN B.
分类号 G09G1/04;H04N3/233;H04N3/26;H04N9/28;(IPC1-7):H01J29/51 主分类号 G09G1/04
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