| 摘要 |
In a frequency synthesizer, the frequency of clock pulses from a voltage controlled oscillator is divided successively with a first scaling factor during a first period of each repetition interval and with a second scaling factor during a second period of the repetition interval to provide output clock pulses at a reduced frequency, the first and second periods being determined in response to a frequency control parameter. A phase comparator detects a phase difference between the output clock pulses and reference frequency pulses and produces pulses with a duration corresponding to the detected phase difference. A canceling circuit produces a canceling pulse with a duration variable as a function of a count value of the output clock pulses and as a function of the frequency control parameter. The canceling pulse is combined with the output pulses of the phase comparator at the input of a loop filter which is connected to the voltage controlled oscillator.
|
