| 摘要 |
Disclosed is an adaptive canceler (32) in which a pipelined approach is used wherein reference signals are divided into two or more sections having concurrent weight adjustment. This architecture allows the speed of adaptive cancellation to be increased and/or the number of reference taps to be increased without loss of cancellation speed. Once a continuous stream of digital data has been established in this architecture, the speed of the adaptive processor is limited only by approximately the processing time of the slowest element. The noise canceled signal may then be converted to the frequency domain in a fast Fourier transform device (34).
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