发明名称 |
Sample and hold circuit and finite impulse response filter constructed therefrom |
摘要 |
A high speed sample and hold circuit comprises an amplifier for producing an output current which is a linear function of an input voltage. A capacitor is responsive to the output current for producing an output voltage representative of the integral of the output current over a predetermined period of time. A switch selectively connects the amplifier to the capacitor during the predetermined period of time. A circuit for discharging the capacitor is also provided. A circuit for producing clock pulses controls the operation of the switch and the discharge circuit. A finite impulse response filter may be constructed around the sample and hold circuit.
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申请公布号 |
US5414311(A) |
申请公布日期 |
1995.05.09 |
申请号 |
US19930121282 |
申请日期 |
1993.09.14 |
申请人 |
CARNEGIE MELLON UNIVERSITY |
发明人 |
CARLEY, L. RICHARD |
分类号 |
G11C27/02;H03F3/00;H03H15/00;(IPC1-7):H03K5/159;H03K5/00;H03K17/16 |
主分类号 |
G11C27/02 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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