发明名称 Error detection and correction apparatus for an asynchronous transfer mode (atm) network device
摘要 An adaptive error detection and correction apparatus for an Asynchronous Transfer Mode (ATM) network device comprises a sensing unit for sensing a congestion condition in the ATM network and a global pacing rate unit for adaptively reducing a maximum allowable transmission ratio of ATM cells containing information to idle ATM cells in response to a sensed congestion condition. A processor stores a number corresponding to a relatively high maximum allowable transmission ratio in the global pacing rate register in the absence of a sensed congestion condition, and stores a number corresponding to a relatively low maximum allowable transmission ratio in the global pacing rate register in response to a sensed congestion condition. A controller adjusts the maximum allowable transmission ratio in accordance with the number stored in the global pacing rate register. A plurality of peak pacing rate counters reset to predetermined values upon decrementation to zero, the predetermined values corresponding to service intervals for segmentation of Conversion Sublayer Payload Data Unit (CD-PDU)s. The processor further comprises means for assigning the counters to selected CD-PDUs, and sensing the counters to determine whether or not segmentation of said selected CD-PDUs is within the respective service intervals. The apparatus further comprises a channel group credit register having bits corresponding to the respective counters.
申请公布号 AU7981494(A) 申请公布日期 1995.05.08
申请号 AU19940079814 申请日期 1994.10.18
申请人 LSI LOGIC CORPORATION 发明人 MICHAEL D ROSTOKER;D. TONY STELLIGA
分类号 H04Q3/00;G06F13/12;H04L12/26;H04L12/56;H04N7/26;H04N7/50;H04N21/2381;H04N21/438;H04N21/61;H04N21/643;H04N21/647;H04Q11/04 主分类号 H04Q3/00
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