发明名称 Serial communications circuit
摘要 A serial communications circuit is constructed in such a way that the secondary CPU (SC) determines the time sequence of bit formats using software, in particular that the secondary CPU (SC) controls a level of each section or an output time sequence of each signal to be output from a unit of data by using software to write specific values to specific registers (3, 4, 6, 95, etc.) and also controls the time sequence of reception, and that the secondary CPU (SC) uses software to control a level of each segment or a time sequence of the acceptance of data of each signal from a unit. By this means, it becomes possible for the serial communications circuit to process processing protocols having different bit formats only by changing the firmware. <IMAGE>
申请公布号 DE4437959(A1) 申请公布日期 1995.05.04
申请号 DE19944437959 申请日期 1994.10.24
申请人 MITSUBISHI DENKI K.K., TOKIO/TOKYO, JP 发明人 TASHIRO, TETSU, ITAMI, HYOGO, JP
分类号 G06F13/00;G06F13/38;H04L29/04;H04L29/08;(IPC1-7):G06F13/38 主分类号 G06F13/00
代理机构 代理人
主权项
地址