PIPELINE READ WRITE OPERATIONS IN A HIGH SPEED FRAME BUFFER SYSTEM

摘要

A frame buffer (17) including an array of memory cells for storing data indicating pixels to be displayed on the output display (18), row addressing decoding apparatus (24) and column address decoding apparatus (26) for selecting memory cells positioned in the array, apparatus (21) for transferring a row address to the row addressing decoding apparatus (24) upon the assertion of a row address strobe signal, apparatus (27) for transferring a column address to the column address decoding apparatus (26) for decoding upon the assertion of a first column address strobe signal, apparatus (32) for latching a column address and any data necessary to complete the access during the first column address strobe signal, apparatus (45) for accessing the particular column the address of which has been latched during the latching of a next subsequent address of a column to be addressed along with any data necessary to complete the next access during the next subsequent column address strobe signal following the first column address strobe signal.