ARCHITECTURE OF OUTPUT SWITCHING CIRCUITRY FOR FRAME BUFFER

摘要

A frame buffer including a plurality of array planes of memory cells (51), row decoding circuitry (52) for selecting rows of memory cells in each of the array planes to be accessed, column decoding circuitry (53) for selecting columns of memory cells in each of the array planes to be accessed, a plurality of bitlines associated with the columns of memory cells of each array plane, each of the bitlines connecting to a column of memory cells and including a bitline sensing amplifier and a column select switch (55) for providing access to the memory cells of that column of the array plane, a plurality of output sense amplifiers (57) adapted to be connected to a selected number of bitlines in an array plane by closing of particular ones of the column select switches in the bitlines, first apparatus for providing output signals from the plurality of output sense amplifiers associated with each array plane to a data bus, and a second apparatus for providing output signals from the plurality of output sense amplifiers associated with each array plane to a shift register (58).