| 发明名称 |
DYNAMIC RAM |
| 摘要 |
Disclosed is a dynamic RAM device capable of initiating and cancelling the test mode in response to the combinations of the row address and column address strobe signals with the write enable signal, which combinations are left unused in the normal operating mode, instead of increasing the number of external control signals. |
| 申请公布号 |
KR950004621(B1) |
申请公布日期 |
1995.05.03 |
| 申请号 |
KR19870003806 |
申请日期 |
1987.04.21 |
| 申请人 |
HITACHI LTD. |
发明人 |
MIYASAWA, KATSUYUKI;SHIMOHIGASHI, KATSUHIRO;EDOU, SHUN;KIMURA, KATSUDAKA |
| 分类号 |
G11C11/401;G01R31/317;G11C29/00;G11C29/14;G11C29/46;(IPC1-7):G11C29/00 |
主分类号 |
G11C11/401 |
| 代理机构 |
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代理人 |
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| 主权项 |
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| 地址 |
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