| 摘要 |
In counter circuitry, for example a motor rotation speed control circuit fabricated in an LSI, a first counter (10), after being reset upon each rotation of the motor, resumes counting clock pulses (CLOCK). Bit-outputs of the first counter (10) are led out of the LSI package and are selectively connected to led-out input terminals of at least one AND gate (18, 12), each of which detects counting, by the first counter (10), of a count-number determined by the sum of the count numbers designated by bit-outputs of the first counter connected to the AND gate. One AND gate (18) detects a first reference count-number Na, which is smaller than a probable least count-number corresponding to, for example, a lower limit of tolerance of motor speed, even taking into consideration possible future changes of the desired motor speed. After being reset upon detection of Na, a second counter (22), preset with a second reference count-number Nb, starts to count the clock pulses. Nb is chosen so that Na + Nb = N0, N0 being a target count-number corresponding to a target cycle time of a single motor rotation. A carry signal from the second counter (22) can be used instead of a signal indicating a count of N0 clock pulses by the first counter (10), even when motor rotation is faster than the target speed. If motor speed has to be modified, the count-numbers for detection can easily be modified by changing the external connections of the led-out terminals. The fixed count-number of the second counter (22) eliminates the need to lead out connections for presetting the second counter, resulting in reduced size and cost of the LSI package. |
