| 摘要 |
Data signals which come from an information source, are transmitted via different transmission paths and to which differential interference signals are added on these paths, must be synchronised and corrected in the receiver. The received data signals are in each case read-in at their respective clock rate into an elastic memory at the receiving end. The common output clock of the elastic memories is set via a phase-locked loop (PLL) in such a manner that read-in and -out address of the memory in the service channel are shifted by 180@ with respect to one another. A synchronisation circuit corrects the relative position of read and write pointers with respect to one another in the alternative channels until the output signals in the alternative channels and in the service channel no longer exhibit a difference in transit time. The error signal of the phase-locked loop is formed from the modular-2 sum of the data signals at the output of the elastic memories. The synchronisation circuit accumulates the error signal over an estimated period of N clock pulses and compares it with a threshold value. If this value is exceeded, loss of synchronisation is assumed and the delay of the signal in the alternative channel is changed by one clock period. If the value drops below the threshold value, that is the synchronised state, the delay remains unchanged. |
