发明名称 PHASE LOCKED LOOP CIRCUIT
摘要 PURPOSE:To obtain an output with reduced a residual phase difference variation and a reduced jitter within a wide VCO voltage range of a voltage control oscillator. CONSTITUTION:In the phase locked loop circuit for allowing a signal of pulse width being proportional to a phase difference of an input signal and an output signal to be subjected to current amplification through a low-pass filter 12, and taking a phase lock, a collector current IC2 of a transistor TR2 is made constant by providing a constant-current load Z to the low-pass filter 12 and fixing a residual phase different amount, and the phase locked loop circuit is operated in the outside of a dead zone so that it is not affected by a set value of an output voltage of a voltage control oscillator 13.
申请公布号 JPH07115363(A) 申请公布日期 1995.05.02
申请号 JP19930258315 申请日期 1993.10.15
申请人 MEIKO:KK 发明人 IKEDA TAKASHI
分类号 H03L7/093;H03L7/08 主分类号 H03L7/093
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