发明名称 |
NON-VOLATILE SEMICONDUCTOR MEMORY |
摘要 |
<p>PURPOSE:To surely write information in a non-volatile memory cell transistor and to shorten the time for writing information. CONSTITUTION:A drain of memory cell transistor Ma1 is connected to a sub-bit line BLsa1 of an EEPROM. The sub-bit line is connected to a main bit line BLa1 through a drain/source of a selection transistor Tsa1. Equivalent capacity Co of the subbit line is previously charged to a potential of the main bit line by temporary ON operation of the selection transistor. A potential of the sub-bit line previously charged is inclined to reduce owing to existence of a leakage current component equivalent resistance Ro, but reduction of a potential of the sub-bit line is prevented by intermittently turning on the selection transistor with a pulse and replenishing electric charges from the main bit line to the sub-bit line.</p> |
申请公布号 |
JPH07114798(A) |
申请公布日期 |
1995.05.02 |
申请号 |
JP19940222734 |
申请日期 |
1994.08.25 |
申请人 |
NKK CORP |
发明人 |
GOTO HIROSHI;ASAKAWA TOSHIBUMI |
分类号 |
G11C17/00;G11C16/02;G11C16/04;G11C16/06;H01L21/8247;H01L27/115;(IPC1-7):G11C16/06 |
主分类号 |
G11C17/00 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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