| 摘要 |
A computer system implementing two levels of translation lookaside buffers (TLBs). The first-level TLBs are small, two-set associative, have a short access time and reside on the CPU chip. The second-level TLBs, on the other hand, are large, direct mapped, and reside in otherwise unused portions of the cache tag RAMs of the instruction and data cache sub-systems. As a result of this arrangement, performance may be improved without limiting the amount of available cache memory for a given implementation. Even if higher capacity memory devices are required for implementing the second-level TLBs in the cache tag RAMs in accordance with the invention, a significant savings over the cost of two sets of smaller devices would still result.
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