摘要 |
An EEPROM enabling high density integration with less power consumption includes source/drain regions formed on the main surface of a P type silicon substrate, and a pair of memory transistors formed therebetween, and a selecting transistor formed between memory transistors and on the main surface of the P type semiconductor substrate. Memory transistors include control gates, and floating gates, respectively. Writing and erasure of data are conducted taking advantage of F-N tunnel phenomenon through tunnel regions.
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