The delay time for forming the carry bit is particularly critical for a high operating speed in the case of full adders. A full adder according to the invention is given a carry bit stage using CMOS technology, which has two current paths which are coupled in the centre and each partial current path of which contains two series-connected MOS transistors. The transistors of the first current path are controlled in pairs by the bit signals which are to be added, and the transistors of the second current path are controlled in pairs by the carry bit of the less-significant stage and the exclusive-OR function of the bit signals. <IMAGE>
