发明名称 ERROR DETECTION AND CORRECTION APPARATUS FOR AN ASYNCHRONOUS TRANSFER MODE (ATM) NETWORK DEVICE
摘要 An adaptive error detection and correction apparatus for an Asynchronous Transfer Mode (ATM) network device (50) comprises a sensing unit (62) for sensing a congestion condition in the ATM network (10) and a global pacing rate unit (58) for adaptively reducing a maximum allowable transmission ratio of ATM cells containing information to idle ATM cells in response to a sensed congestion condition. A processor (52) stores a number corresponding to a relatively high maximum allowable transmission ratio in the global pacing rate register (58c) in the absence of a sensed congestion condition, and stores a number corresponding to a relatively low maximum allowable transmission ratio in the global pacing rate register (58c) in response to a sensed congestion condition.
申请公布号 WO9511554(A1) 申请公布日期 1995.04.27
申请号 WO1994US11788 申请日期 1994.10.18
申请人 LSI LOGIC CORPORATION 发明人 ROSTOKER, MICHAEL, D.;STELLIGA, D., TONY
分类号 H04Q3/00;G06F13/12;H04L12/26;H04L12/56;H04N7/26;H04N7/50;H04N21/2381;H04N21/438;H04N21/61;H04N21/643;H04N21/647;H04Q11/04;(IPC1-7):H04J3/14 主分类号 H04Q3/00
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