| 摘要 |
The leading zero-suppression/symbol encoding circuit includes a parallel input parallel output (PIPO) shift register for performing a leading zero-suppression through parallel inputting data which a microprocessor outputs by one byte and through parallel outputting it by two bytes, a parallel input serial output (PISO) shift register for generating clock periods of 1 unit symbol time (UST) and 2 UST for processing symbol encoding of data, a data load control unit for controlling a data load of PIPO and PISO shift registers, a logic decision unit for deciding that every data of each bit is logic 0, a latch for storing and outputting a mode signal output from the microprocessor, a clock frequency demultiplier for outputting 2MHz system clock signal after frequency-demultiplying of 8MHz system clock signal, a counter unit for generating various UST after detecting the mode signal from the latch, an interrupt generating unit for making the microprocessor output the data and mode signal of new field, and a load/reset control unit for resetting the clock frequency demultiplier.
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