| 摘要 |
PCT No. PCT/DE93/00516 Sec. 371 Date Dec. 6, 1994 Sec. 102(e) Date Dec. 6, 1994 PCT Filed Jun. 15, 1993 PCT Pub. No. WO94/01891 PCT Pub. Date Jan. 20, 1994.To produce storage capacitors for DRAM cells, dummies (81) of SiO2 which are disposed in accordance with the negative pattern of the storage node arrangement (91) are formed using auxiliary layers of SiO2 and polysilicon. The storage nodes (91) are formed, by depositing a doped polysilicon layer over the entire surface and structuring it, in such a way that they cover the area inside the dummies (81) and the side walls of the dummies (81) and that the surface of the dummies (81) is exposed in their upper region. After removing the dummies (81), a storage dielectric and a cell plate are formed. The process can be used in the production of a stacked-capacitor DRAM cell. |
