| 摘要 |
The present invention realizes page mode memory access in a single clock memory. A control signal PAGE, one level of which designates an ordinary mode and the other level of which designates a page mode, is provided to a single clock memory from the outside. A mode state identification circuit identifies four mode states, ordinary mode, page-in, during-page, and page-out, by decoding the combination of the control signal levels in two consecutive memory cycles. A memory control circuit part of a memory array is thereby controlled based on the result of the identification.
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