发明名称 |
PLL frequency synthesizer circuit |
摘要 |
A reference frequency divider divides a clock signal into a reference frequency signal, and outputs it. A comparison frequency divider circuit divides an output signal from a voltage controlled oscillator, and outputs it as a comparison signal. The reference signal and comparison signal are coupled to a phase comparator. The phase comparator detects the phase difference between the reference signal and comparison signal, and outputs a phase difference signal. A charge pump outputs a voltage signal in response to the phase difference signal from the phase comparator. A low pass filter smooths out the voltage signal from the charge pump to remove the high frequency components, and outputs a controlled voltage signal. A voltage controlled oscillator outputs an output signal with the frequency relating to the voltage value of the controlled voltage signal from the low pass filter. A frequency difference determining circuit compares the reference signal with the comparison signal. The circuit outputs a signal indicative of the frequency locked when the frequency difference is within the preset range, and outputs a signal indicative of the frequency unlocked when the difference of the frequency exceeds the preset range.
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申请公布号 |
US5410571(A) |
申请公布日期 |
1995.04.25 |
申请号 |
US19930121546 |
申请日期 |
1993.09.16 |
申请人 |
FUJITSU LIMITED;FUJITSU VSLI LIMITED |
发明人 |
YONEKAWA, MASAYUKI;AKIYAMA, TAKEHIRO;SAITO, SHINJI;AISAKA, TETSUYA;TAKAGI, MINORU |
分类号 |
H03L7/089;H03L7/095;H03L7/107;H03L7/183;(IPC1-7):H03D3/24 |
主分类号 |
H03L7/089 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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