摘要 |
The carry propagation delay of a manch ester carry chain adder is reduced by using the wired-logical parallel transistors and a tri-state buffer. The circuit comprises a carry propagation signal input terminal (21) for receiving the carry propagation signal using the N-MOS transisters connected in parallel, a tri-state inverter (22) turned on or off according the input carry and input/output status of an inverter (I1), a tri-state inverter (23) controlled by the output signal of the tri-state buffer (22) and clock signal, and a PMOS transister (PT) for charging the input node of the inverter (I1).
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