| 摘要 |
<p>PURPOSE:To reduce man-hour for the preparation of a test pattern for user logic by preventing a user logic function from being remarkably limited even when user logic is designed synchronously with an operation clock independent of the operation clock of a single chip microcomputer. CONSTITUTION:An external bus I/F port 1 is utilized as a general port when an external bus is not used and operates so as to connect a single chip microcomputer core 4 to an external integrated circuit in accordance with a control signal from the core 4. A bus I/F 2 generates a signal and timing for connecting an asynchrous external bus similarly to the I/F port 1 and connects the core 4 to user logic 3 or connects the user logic 3 to the external through the port 1 in accordance with a test signal inputted from the external.</p> |
