| 摘要 |
PURPOSE:To reduce the load for a bit line and to relax a condition for restricting an area of layout in a semiconductor memory having hierarchical bit line structure. CONSTITUTION:Main bit lines MBL and ZMBL are arranged at both sides of a sense amplifier SA. One main bit lines MBL and ZMBL are provided for sub-bit lines SBL1, SBL2 and SBL3, SBL4 making a pair respectively. A sub-bit line pair of SBL1, SBL2 is connected to the main bit line MBL through a block selecting switch T1. A sub-bit line pair of SBL3, SBL4 is connected to the main bit line ZMBL through a block selecting switch T2. Since one bit line is provide for two sub-bit lines, a pitch of the main bit line is made two times as much as the sub-bit line, a condition for a pitch of the main bit line is largely relaxed, layout of elements can be made easy. |
