ADDRESS SIGNAL DELAY GENERATING CIRCUIT FOR IMAGE MOTION COMPENSATION

摘要

The circuit comprises; means for providing delay amount data of a write address signal of a frame memories; delay control means for determining a delay amount from the delay amount data and providing a delay control signal for delaying the write address signal; address counter means for counting a system clock so as to provide the write address signal in accordance with the delay control signal; latch means for synchronizing the write address signal provided from the address counter means by temporarily storing the write address signal; and a multiplexer for selectively applying the write address signal having passed through the latch means to one of the frame memories in accordance with a frame synchronizing signal so that image data per frame is selectively written in one of the frame memories.