| 摘要 |
A method for determining test pattern fault equivalence. The method comprises selecting a bridging fault (16) from a digital circuit, then determining a stuck-at fault (17) which guarantees detection of the bridging fault. Generation of a test vector (18) which detects the stuck-at fault. Simulating the test vector (19) to find all bridging faults that are detected by the test vector, and repeating the above steps until the desired percentage of detectable bridging faults are examined.
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