发明名称 SHIFT CIRCUIT AND VARIABLE LENGTH ENCODER AND DECODER
摘要 PURPOSE:To make the data lines of barrel shifters into small amplitude and effectively use the barrel shifter in area by forming first and second barrel shifters by planarly combining them with each other and directly connecting the barrel shifters without providing a pipeline register. CONSTITUTION:In a shift circuit 3A, the output of a first barrel shifter BSA 0 is directly added to a second barrel shifter BSA1 by providing a register (a flip-flop for which a sense up is used.) R3A0 on the only output side of a second barrel shifter BSA1 without providing a pipeline register between a first barrel shifter BSA0 and the second barrel shifter BSA1. The first and second barrel shifters BSA0 and BSA1 are formed in a superposed state in patterns. Thus, area to spare is provided, one data line can be made for 1-bit from the input end of the first barrel shifter to the output end of the second barrel shifter and the making the data line into small amplitude becomes possible.
申请公布号 JPH07104973(A) 申请公布日期 1995.04.21
申请号 JP19930245380 申请日期 1993.09.30
申请人 TOSHIBA CORP 发明人 SHIMAZAWA TAKAMI;SETA KATSUHIRO;MATSUI MASAKI
分类号 G06F7/00;G06F5/01;G06F7/76;H03M7/40 主分类号 G06F7/00
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