| 摘要 |
PURPOSE:To improve the low speed of an integration circuit due to the carry operation time of an adder and to sufficiently cope with a high speed operation. CONSTITUTION:This circuit is provided with a first adder 1 performing the integration of even-numbered data and a second adder 2 performing the integration of odd-numbered data. The addition result of this even-numbered data is temporarily stored in first registers 3 and 5, the addition result of the odd- numbered data is temporarily stored in second registers 4 and 6. The circuit is provided with the third and fourth adders 7 and 8 adding the integration result of the temporarily stored even--numbered data and the integration result of the odd-numbered data. The integration results of the adders 7 and 8 are alternately switched by a switching device 9 and the integration result of the sum total of all data is outputted. |
