| 摘要 |
PURPOSE:To provide a clock regenerating circuit which can control the phase of the sampling clock of a video signal and can perform an accurate sampling operation. CONSTITUTION:A signal of frequency f0 is sent to an n1-divider 2 from an oscillator 1, and the n1-divider 2 starts its n1-division synchronously with a horizontal synchronizing signal Hs. A PLL circuit 10 consists of a phase comparator 5, an LPF 6, a voltage control oscillator 7 and an n2-divider 8. As the frequency of the n1-divider output is f0/n1, the output frequency of a clock regenerating circuit is equal to (n2/n1).f0. The phase of a reproduced clock is controlled by changing the division starting position of the n1-divider 2. Meanwhile the output frequency of the clock regenerating circuit is controlled by changing the division number n1 and n2. |
