| 摘要 |
PURPOSE: To provide a core cell having the transistor layout with which a memory circuit can be designed efficiently in a gate array circuit. CONSTITUTION: A core cell contains a plurality of the first conductive type of the first transistors 14 to 22, the second transistors 23 to 31 and the second conductive type of the third transistors 52 to 63, and the third plurality of transistors are positioned between the first and the second pluralities of transistors. The third plurality of transistors have the first and the second size transistors, and at least two of the second size transistors in the third plurality of transistors have a common gate connection part. |
