发明名称 Parallel data processing system with plural-system bus configuration capable of fast data communication between processors by using common buses
摘要 In a parallel computer system in which many microprocessor elements are disposed at least in a two dimensional array to communicate data therebetween at a high speed, n bidirectional buses XBi and m bidirectional YBi are respectively arranged in X and Y directions to dispose m by n data processor elements CPUij at intersections of the buses XBi and YBj, thereby connecting these elements respectively to the associated buses XBi and YBj. Each processor element has a unit for selectively establishing a connection between the bus XBi and the bus YBj which are coupled thereto. In a data transfer between two elements sharing neither one of the bidirectional buses in the X and Y directions, there is selected an element which is connected to one of the X-directional-buses linked to one of the elements and which is connected to, one of the Y-directional buses linked to the other one thereof to use the selected element as a relay for establishing a conductive route between the buses.
申请公布号 US5408676(A) 申请公布日期 1995.04.18
申请号 US19920998532 申请日期 1992.12.30
申请人 HITACHI, LTD. 发明人 MORI, KAZUTAKA
分类号 G06F15/16;G06F15/173;G06F15/80;(IPC1-7):G06F13/00 主分类号 G06F15/16
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