发明名称 |
Phase delay compensator using gating signal generated by a synchronizer for loading and shifting of bit pattern to produce clock phases corresponding to frequency changes |
摘要 |
A phase delay compensator apparatus is provided which compensates for the phase error caused by propagation delay differences between clock and data paths within a computer system. A look-up table circuit is used to dynamically translate a change in frequency of the computer system clock or a change in the length of cable connecting the computer's sub-assemblies to a binary bit pattern defining the requisite phase-shift between distributed clock and data signals. A generator circuit produces phases of the phase-shifted clock signals, while ensuring the integrity of the loaded binary bit pattern. A gated signal is created for enabling the generator circuit.
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申请公布号 |
US5408640(A) |
申请公布日期 |
1995.04.18 |
申请号 |
US19920995311 |
申请日期 |
1992.12.22 |
申请人 |
DIGITAL EQUIPMENT CORPORATION |
发明人 |
MACINTYRE, DOUGLAS A.;HAWKINS, THOMAS B. |
分类号 |
G06F1/08;(IPC1-7):G06F1/04;G06F1/06;G06F1/12 |
主分类号 |
G06F1/08 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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