| 摘要 |
Address data supplied from a system or the like is output to a storage memory constituting transfer destination and source memories as row and column address from an upper bit side in a normal memory access mode. In only a DMA operation mode, a value obtained by multiplying 2n with the supplied address value is output to the storage memory as an output address value, and values from "0" to "2n-1" are sequentially and automatically output to the memory as lower n bits, i.e., lower n bits of a column address. During this interval, the system is requested to prolong one bus cycle. Peripheral sections as objects of DMA transfer have a data buffer corresponding to at least 2n words. A peripheral section for outputting data to the memory outputs a DMA request after at least 2n data are present in the buffer. A peripheral section for receiving data from the memory outputs a DMA request when the buffer has an empty area corresponding to at least 2n data. These peripheral sections are arranged to output or receive 2n-word data in accordance with a timing signal which is output from an address controller in synchronism with a change in lower n-bit address, thereby performing access in the high-speed page mode.
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