| 摘要 |
Parallel metallization lines for a substrate of an electronic device, such as complementary bit (B and &upbar& B) lines for an SRAM cell array, are formed by: forming a uniformly thick aluminum layer with an underlying and overlying dielectric oxide layer, the underlying oxide layer being located overlying the substrate, patterning the overlying oxide and the aluminum layers to form the aluminum bit line (B) with an overlying dielectric oxide layer on its top surface, typically by means of reactive ion etching, depositing a further dielectric oxide layer on the entire surface of the structure including the sidewalls of the aluminum bit line (B), and reactive ion etching the top surface of the oxide layer, whereby an oxide layer remains on the top and sidewall surfaces of the aluminum bit line (B) but not elsewhere. Subsequent forming of a second uniformly thick aluminum layer on the top surface of the structure that is being fabricated, followed by patterning this second aluminum layer, forms the complementary aluminum bit line ( &upbar& B).
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