| 摘要 |
PCT No. PCT/DE91/00957 Sec. 371 Date Jul. 9, 1993 Sec. 102(e) Date Jul. 9, 1993 PCT Filed Dec. 10, 1991 PCT Pub. No. WO92/12518 PCT Pub. Date Jul. 23, 1992.In the memory cell arrangement, each memory cell consists of a field-effect transistor comprising a gate dielectric (14) which contains at least one ferroelectric layer (142). Depending on the sign of the remanent polarization of the ferroelectric layer (142), the field-effect transistor exhibits one of two different threshold voltages which have the same sign and which are allocated to the logic states "0" and "1". Information is written in by repolarizing the ferroelectric layer (142), information items are read by applying a voltage to the gate electrode of the field-effect transistor, the voltage being between the two threshold voltages. |
