Circuit for monitoring voltage lines and at least one clock line of an integrated digital circuit

摘要

A circuit is proposed which tests the operational state of voltage lines and at least one clock line of an integrated digital circuit. The circuit comprises a T-flipflop with two voltage inputs, clock inputs, a data input and an inverted data output. The voltage lines to be tested are fed to the voltage inputs of the T-flipflop. The clock line to be tested is fed back to the clock input of the T-flipflop. If the voltage lines and the clock line and the clock generator are functional, the data output of the T-flipflop outputs an oscillating signal. If one voltage line or the clock line is defective, the data output of the T-flipflop outputs a constant signal which is detected by an evaluation circuit.