发明名称
摘要 PURPOSE:To improve the reliability by generating a congestion signal at any faulty state either operation congestion of a programmable controller o a couple of CPUs to eliminate the generation of an erroneous arithmetic congestion signal. CONSTITUTION:An identical signal stored in main, sub CPUs 3a, 3b operates a clock 2, a programmable controller 1 makes sequence arithmetic in response to the sequence time counted by the clock 2, and when the arithmetic is finished, the clock 2 and the controller 1 are reset by the command of the CPU 3a, 3b. On the other hand, if the sequence arithmetic by the controller 1 is congested and the arithmetic of each step is not executed within a prescribed time, a signal is transmitted to an OR circuit 4 via a line B to raise an arithmetic congestion signal E. If any of the CPU 3a, 3b is faulty, a signal is transmitted to the circuit 4 via the lines C, D to raise the signal E.
申请公布号 JPH0731544(B2) 申请公布日期 1995.04.10
申请号 JP19840206986 申请日期 1984.10.04
申请人 发明人
分类号 G05B23/02;G05B19/02;G05B19/042;G05B19/048;G05B19/05 主分类号 G05B23/02
代理机构 代理人
主权项
地址