发明名称
摘要 <p>PURPOSE:To prevent an index signal unerased from being detected by taking out only the index signal, which is outputted in the period when a gate is opened, by a window pulse obtained from an area designating signal generating means. CONSTITUTION:When FM digital data FMDT inputted to an index detecting part 60 and a clock signal CLK are inputted to a demodulating circuit 61, NRZ data where parts of '1' and parts of '0' of data are set to a high level and a low level respectively is outputted. This data is inputted to a '0' detecting part 62 and a '1' detecting part 63, and a pulse is outputted in a '1' detection signal S1 if '1' continues for a timer tau1, and a pulse is outputted in a '0' detection signal S0 if '0' continues for a time tau0. If a period T of a postamble part 14 having a pulse width tauM to be the second window pulse PM is set to satisfy T+tau0>tau1+tauM>T, a pulse P5 cannot pass an AND gate 68 even if an index signal IS' unerased is outputted as the pulse P5 after the time tau1.</p>
申请公布号 JPH0731879(B2) 申请公布日期 1995.04.10
申请号 JP19860185230 申请日期 1986.08.08
申请人 发明人
分类号 G11B20/10;G11B15/087;(IPC1-7):G11B20/10 主分类号 G11B20/10
代理机构 代理人
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