| 摘要 |
System speed boundary tests are made on nets interconnecting field programmable logic without any external testing equipment or special printed circuit board layout for such a test. Only a single net interconnecting all field programmable logic in a ring is employed. The tests are made for opens and shorts and localize faults to a particular net. Nets interconnecting field programmable logic are tested utilizing the information stored in the circuit design file and the reprogrammability of the field programmable logic to construct a circuit that is then implemented in the field programmable logic and tests all interconnecting nets. |
