发明名称
摘要 A method for producing a mask pattern for a semiconductor integrated circuit includes dividing the mask pattern data into a plurality of lower level cells and an upper level cell having wiring lines for providing connections between the lower level cells, extracting inter-cell connection information from the mask pattern data, changing the dimensions of the lower level cells by predetermined ratios to conform to a design standard, and changing the wiring lines of the upper level cell to retain the connection between the lower level cells in accordance with the inter-cell connection information extracted.
申请公布号 JPH0731695(B2) 申请公布日期 1995.04.10
申请号 JP19880268121 申请日期 1988.10.26
申请人 发明人
分类号 H01L21/822;G06F17/50;H01L21/027;H01L21/30;H01L21/82;H01L27/02;H01L27/04;(IPC1-7):G06F17/50 主分类号 H01L21/822
代理机构 代理人
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