| 摘要 |
PURPOSE:To obtain the delaying circuit which can be constituted at a comparatively low cost by only a digital circuit, and also, can obtain an exact delay time. CONSTITUTION:A delay time of each element of an integrated circuit is set as a delay element and those delay elements 102, 103, 104 and 105 are set to a state connected in series, and the output of each delay element is inputted to a second multiplexer 106 and a D-flip-flop assembly 109. A control means 108 selects first a clock CK whose frequency is known by a first multiplexer 101. From each Q0, Q1, Q2 and QN signal of the D-flip-flop assembly 109, a delay time per one piece of delay element is calculated, and the delay element to select an output is determined so as to become a necessary delay time and instructed to a second multiplexer 106. Subsequently, in a first multiplexer 101, an input signal SIN to be delayed is selected and inputted. |
