| 摘要 |
PURPOSE:To constitute the delaying circuit so that only a rise time of an output signal is lengthened, and a fall time is scarcely lengthened. CONSTITUTION:This delaying circuit is provided with two inverters 1 and 2, and a P channel MOS capacitor 4, the source electrode of a P channel MOS transistor 2a of the inverter 2 is connected to the output node of the inverter 1, and the capacitor 4 is connected between an output node 1c of the inverter 1 and a ground node 200. When an output signal Sout rises, the capacitor 4 is charged, therefore, the output signal Sout ascends gradually, but when the output signal Sout falls, the P channel MOS transistor 2a of the inverter 2 becomes a non-conducting state, and an N channel MOS transistor 2b also becomes a conducting state, so that the output signal Sout descends quickly. |
