| 摘要 |
PURPOSE:To decrease a decoding error generated at the time of decoding a signal. CONSTITUTION:An equalizer 4 which integrates and equalizes a reproduced signal is provided, while in order to decode a signal based on this integration and equalization, a first data detecting means constituted of an operation processing circuit 6 and a viterbi decoder 7 end a second data detecting means which is constituted of a digital comparator 8 and an operation processing circuit 9 and has an integration detecting system are provided. And viterbi decoding can be performed using data having less error based on a binary integration and equalization signal by selecting a decoding data obtained by the second data detecting means by a data selector 10 at the time of specific reproducing base on a control signal s1 of a reproducing mode given by a system controller 13. While, even when a level of the reproduced signal is largely varied, a decoding error factor is not increased and good digital reproduction can be performed. |
